1. Field of the Invention
The present invention relates to a CML-CMOS conversion circuit that converts the voltage amplitude of a CML (Current Mode Logic) circuit to the voltage amplitude of a CMOS (Complementary Metal Oxide Semiconductor) circuit.
2. Description of the Related Art
In devices such as portable terminals that operate on one battery, recent years have seen a growing demand not only for lower power consumption but for the higher-speed operation that accompanies higher frequencies of used lines. Circuits incorporated in these types of devices therefore have adopted a BICMOS (Bipolar-CMOS) configuration in which bipolar transistors capable of high-speed operation and CMOS (Complementary Metal-Oxide Semiconductor) circuits that are more advantageous for lower power consumption are formed on the same chip. There has consequently been a need for CML-CMOS conversion circuits in circuits in which the BICMOS configuration is adopted, these CML-CMOS conversion circuits serving as interface circuits between CML (Current Mode Logic) circuits that are formed by bipolar transistors and that operate at CML amplitude and CMOS circuits that operate at CMOS logic amplitude. One example of such a CML-CMOS conversion circuit is shown in FIG. 1.
In FIG. 1, differential circuit 20 is constituted by two bipolar transistors Q201 and Q202 having emitters connected in common, the emitter of bipolar transistor Q201 and the emitter of bipolar transistor Q202 each being connected to ground potential GND by way of resistor R203, which determines the current flowing in each. While FIG. 1 shows a configuration in which the current flowing in differential circuit 20 is determined by resistor R203, a constant-current regulated power supply circuit that is made up of transistors may also be used in place of resistor R203. The collector of bipolar transistor Q201 is a first differential output terminal 21 and is connected to power supply VDD by way of resistor R201. The collector of bipolar transistor Q202 is a second differential output terminal 22 and is connected to power supply VDD by way of resistor R202.
In addition, second differential output terminal 22 is connected to ground potential GND by way of bipolar transistor Q203 in which the collector and base are connected. Current mirror circuit 24 is formed by connecting in common the bases of bipolar transistor Q203 and bipolar transistor Q204. The emitter of bipolar transistor Q204 is grounded, and the collector of bipolar transistor Q204 is connected to power supply VDD by way of resistor R204.
The collector of bipolar transistor Q204 is connected to output terminal OUT, and output terminal OUT is connected to the input of CMOS inverter 27, which is made up of p-channel MOS transistor M202 and n-channel MOS transistor M201.
Explanation is next presented regarding the operation of the CML-CMOS conversion circuit shown in FIG. 1 and having the above-described configuration.
First, when a high-level signal is inputted at CML amplitude to positive input terminal IN of differential circuit 20 and a low-level signal is inputted at CML amplitude to inverted input terminal INB of differential circuit 20, bipolar transistor Q201 connected to positive input terminal IN enters a conductive state, and bipolar transistor Q202 connected to inverted input terminal INB enters a nonconductive state, whereupon current flows to bipolar transistor Q201 from power supply VDD by way of resistor R201, which is load resistance, and a low-level signal is outputted from first differential output terminal 21. In addition, since bipolar transistor Q202 is in a nonconductive state, a high-level signal is outputted from second differential output terminal 22, bipolar transistor Q203 and bipolar transistor Q204 each enter a conductive state, and a low-level signal is outputted from output terminal OUT.
On the other hand, when a low-level signal at CML amplitude is inputted to positive input terminal IN of differential circuit 20 and a high-level signal at CML amplitude is inputted to inverted input terminal INB of differential circuit 20, bipolar transistor Q201 connected to positive input terminal IN enters a nonconductive state and bipolar transistor Q202 connected to inverted input terminal INB enters a conductive state. In this case, current flows to bipolar transistor Q202 from power supply VDD by way of resistor R202, which is load resistance, and a low-level signal is outputted from second differential output terminal 22. In addition, since bipolar transistor Q201 is in a nonconductive state, a high-level signal is outputted from first differential output terminal 21. When a low-level signal is outputted from second differential output terminal 22, bipolar transistors Q203 and Q204 each enter a nonconductive state and a high-level signal is outputted from output terminal OUT.
CMOS inverter 27 outputs a high-level signal at CMOS logic amplitude when output terminal OUT is at low level, and outputs a low-level signal at CMOS logic amplitude when output terminal OUT is at high level.
Explanation is next presented regarding another CML-CMOS conversion circuit of the prior art with reference to FIG. 2.
In FIG. 2, differential circuit 30 is made up of two bipolar transistors Q301 and Q302 having emitters connected in common, and the emitter of bipolar transistor Q301 and the emitter of bipolar transistor Q302 are connected to ground potential GND by way of resistor R301, which determines the current flowing to each. FIG. 2 shows a configuration in which the current that flows to differential circuit 30 is determined by resistor R301, but a constant-current regulated power supply circuit that is made up of transistors may also be used in place of resistor R301. The collector of bipolar transistor Q301 (first differential output terminal 31) is connected to power supply VDD by way of p-channel MOS transistor M301 in which the gate and drain are connected, and the collector of bipolar transistor Q302 (second differential output terminal 32) is connected to power supply VDD by way of p-channel MOS transistor M302 in which the gate and drain are connected.
Connecting the gate of p-channel MOS transistor M301 in common with the gate of p-channel MOS transistor M303 produces first current mirror circuit 34. The source of p-channel MOS transistor M303 is connected to power supply VDD, and the drain of p-channel MOS transistor M303 is connected to ground potential GND by way of n-channel MOS transistor M305 in which the drain and gate are connected.
In addition, connecting the gate of p-channel MOS transistor M302 in common with the gate of p-channel MOS transistor M304 produces second current mirror circuit 35. The source of p-channel MOS transistor M304 is connected to power supply VDD, and the drain of p-channel MOS transistor M304 is connected to ground potential GND by way of n-channel MOS transistor M306. With their gates connected in common, n-channel MOS transistor M305 and n-channel MOS transistor M306 make up third current mirror circuit 36.
The drain of p-channel MOS transistor M304 is connected to output terminal OUT, and output terminal OUT is connected to the input of CMOS inverter 37, which is made up from p-channel MOS transistor M308 and n-channel MOS transistor M307.
Next, regarding the operation of the CML-CMOS conversion circuit shown in FIG. 2 configured as described hereinabove, first, when a high-level signal at CML amplitude is inputted to positive input terminal IN of differential circuit 30 and a low-level signal at CML amplitude is inputted to inverted input terminal INB, bipolar transistor Q301 connected to positive input terminal IN enters a conductive state and bipolar transistor Q302 connected to inverted input terminal INB enters a nonconductive state. Since bipolar transistor Q302 is in a nonconductive state, a high-level signal is then outputted from second differential output terminal 32 and p-channel MOS transistors M302 and M304 both enter a nonconductive state. In addition, because bipolar transistor Q301 is in a conductive state, a low-level signal is outputted from first differential output terminal 31, p-channel MOS transistors M301 and M303 both enter a conductive state, and a high-level signal is outputted from the drain (terminal 33) of p-channel MOS transistor M303. Accordingly, n-channel MOS transistors M305 and M306 both enter a conductive state, and a low-level signal is outputted from output terminal OUT.
On the other hand, when a low-level signal at CML amplitude is inputted to positive input terminal IN of differential circuit 30 and a high-level signal at CML amplitude is inputted to inverted input terminal INB, bipolar transistor Q301 connected to positive input terminal IN enters a nonconductive state and bipolar transistor Q302 connected to inverted input terminal INB enters a conductive state. A high-level signal is then outputted from first differential output terminal 31, each of p-channel MOS transistors M301 and M303 enter a nonconductive state, and each of n-channel MOS transistors M305 and M306 enters a nonconductive state. In addition, since bipolar transistor Q302 is in a conductive state, a low-level signal is outputted from second differential output terminal 32, p-channel MOS transistors M302 and M304 both enter a conductive state, and a high-level signal is outputted from output terminal OUT.
CMOS inverter 37 outputs a high-level signal at CMOS logic amplitude when output terminal OUT is at low level, and outputs a low-level signal at CMOS logic amplitude when output terminal OUT is at high level.
In the CML-CMOS conversion circuit shown in FIG. 2, variations occur in the current flowing to differential circuit 30 because MOS transistors are connected to the output of differential circuit 30. Nevertheless, the voltage amplitude inputted to CMOS inverter 37 is stable because the output voltage of output terminal OUT is determined by the conductive/nonconductive states of p-channel MOS transistor M304 and n-channel MOS transistor M306.
The threshold voltage V.sub.T of a CMOS transistor is generally 0.55 [V] for an n-channel MOS transistor and 0.65 [V] for a p-channel MOS transistor, with a variation originating in fabrication of .+-.10.15 [V].
In addition, the direct-current current amplification factor h.sub.FE of a bipolar transistor is on the order of 100 at typical value (typical value), with a variation of 1/2 to double the typical value originating in fabrication. Moreover, variation in the resistance of resistors resulting in fabrication is on the order of .+-.15% the typical value.
The effect on the CML-CMOS conversion circuits of the prior art shown in FIG. 1 and FIG. 2 resulting from such variation for each circuit element is next examined, beginning with an examination of the effect on the CML-CMOS conversion circuit shown in FIG. 1.
In the CML-CMOS conversion circuit shown in FIG. 1, output signals are received from only one of the differential output terminals (second differential output terminal 22) of differential circuit 20. In such a case, the output voltage of output terminal OUT is determined by the output voltage of second differential output terminal 22, and as a result, higher accuracy is demanded of each circuit element than in a configuration in which output signals are taken from each of two differential output terminals 31 and 32 as in the CML-CMOS conversion circuit shown in FIG. 2. In particular, variation originating in fabrication in the threshold voltage V.sub.T of the MOS transistors has the greatest effect on operation of the CMOS inverter.
As described hereinabove, the maximum variation in threshold voltage V.sub.T is 0.55 [V]+0.15 [V]=0.70 [V] for an n-channel MOS transistor and 0.65 [V]+0.15 [V]=0.80 [V] for a p-channel MOS transistor.
In this case, in order for CMOS inverter 27 to operate when the voltage of power supply VDD is 1.0 [V], the output voltage of output terminal OUT must be made 0.2 [V] or less and p-channel MOS transistor M202 be placed in a conductive state, and, the output voltage of output terminal OUT must be made 0.7 [V] or greater and n-channel MOS transistor M201 be placed in a conductive state.
When the voltage V.sub.CE across the collector and emitter of bipolar transistor Q204 is 0.2 [V] or less, however, bipolar transistor Q204 operates in a saturated state. As a result, conduction by the parasitic pnp transistor allows current to flow to the substrate, thereby causing a decrease in the apparent direct-current current amplification factor h.sub.FE and a drop in the frequency characteristic, and high-speed operation is prevented.
In addition, latch-up occurs when current flows to the parasitic pnp transistor because the potential of the substrate becomes higher than the ground potential.
However, in the configuration of CML-CMOS conversion circuit shown in FIG. 1, enlarging the transistor size of p-channel MOS transistor M202 in CMOS inverter 27 and increasing the drain current enables p-channel MOS transistor M202 to be placed in a conductive state even if the output voltage of output terminal OUT is not 0.2 [V] or less.
Nevertheless, increasing the transistor size causes more current than necessary to flow to CMOS inverter 27, and this in turn causes the frequency characteristic to drop due to the capacitance of the p-channel MOS transistor itself, and high-speed operation is therefore prevented.
If the resistance value of resistor R204 is set such that the current (conductive state) flowing to bipolar transistor Q204 is 10 [.mu.A] at the typical value, direct-current current amplification factor h.sub.FE becomes 1/2 the typical value when at a minimum, whereby the minimum current flowing to bipolar transistor Q204 becomes 5 [.mu.A]. The voltage drop of resistor R204 must then be made 0.8 [V] or more in order to place p-channel MOS transistor M202 in a conductive state.
In other words, the resistance of resistor R204 becomes: EQU 0.8 [V]/5 [.mu.A]=160 [K.OMEGA.].
In such a case, if variations in resistance are taken into consideration, the value of resistor R204 must be made: EQU 160 [K.OMEGA.](typical value)/0.85(variation)=188 [K.OMEGA.]
If resistor R204 is made 188 [K.OMEGA.], however, the occurrence of variations in the direction of increase in direct-current current amplification factor h.sub.FE and the resistance value may cause the voltage drop due to resistor R204 to become: 20 [.mu.A] {2(variation in direct-current current amplification factor h.sub.FE).times.10 [.mu.A]}.times.216 [k.OMEGA.]{188 [K.OMEGA.].times.1.15(variation of the resistance value)}=4.32 [V]. As a result, only low level is outputted from output terminal OUT, and moreover, bipolar transistor Q204 operates in a saturated state, whereby the frequency characteristic drops and high-speed operation becomes impossible.
As described hereinabove, in the configuration shown in FIG. 1, the output voltage of output terminal OUT is determined by the resistance value of resistor R204 and the current flowing to the resistor. As a consequence, the resulting circuit is highly sensitive to fluctuations in the values of resistor R 204 and the direct-current current amplification factor h.sub.FE of bipolar transistor Q204.
In addition, because bipolar transistor Q204 operates in a saturated state, there is the problem that the frequency characteristic of the CML-CMOS conversion circuit drops precipitously and high-speed operation is prevented.
On the other hand, in the CML-CMOS conversion circuit shown in FIG. 2, p-channel MOS transistors are employed as the load of differential circuit 30, and as a result, when large variation occurs in the threshold voltage V.sub.T of p-channel MOS transistors M301 and M302 (a maximum of 0.8 [V], the output voltage (when bipolar transistors Q301 and Q302 are in a conductive state) of first differential output terminal 31 and second differential output terminal 32 must be made 0.2 [V] when the voltage of power supply VDD is made 1. Bipolar transistors Q301 and Q302 then operate in a saturated state, whereby a drastic drop occurs in the frequency characteristic and high-speed operation is prevented.
However, enlarging the transistor size of p-channel MOS transistors M301 and M302 and increasing the drain current allows operation without problems despite a high output voltage of first differential output terminal 31 and second differential output terminal 32 (when bipolar transistors Q301 and Q302 are in a conductive state). Nevertheless, the capacitance of the p-channel MOS transistors themselves increases in such a case, whereby the frequency characteristic drops and high-speed operation is prevented.
Decreasing the gain of differential circuit 30 can be considered as one method of improving the frequency characteristic. In such a case, the current flowing to p-channel MOS transistors M301 and M302 decreases and problem-free operation is enabled despite high output voltage of first differential output terminal 31 and second differential output terminal 32 (when bipolar transistors Q301 and Q302 are in a conductive state). Nevertheless, the decrease in current flowing to bipolar transistors Q301 and Q302 of differential circuit 30 in this case causes the frequency characteristic of differential circuit 30 to drop and prevents high-speed operation.
In other words, in the CML-CMOS conversion circuit of the prior art shown in FIG. 1 and FIG. 2, there is the problem that, due to the effect of variations in circuit elements, a drastic drop occurs in the frequency characteristic and high-speed operation is rendered impossible in cases in which the power supply voltage is low (for example, if the battery voltage is 1 [V]. In addition, there is the problem that the transistors making up the circuit may cause latch-up.